The present invention relates to a clock control circuit which has a delay array and which is designed to control the timing of an external clock generated by a CPU and the timing of an internal clock signal used in a memory (IC).
Most of the memories recently developed are of the type which transfers data at high speed in synchronism with clock signals. A synchronous DRAM (namely, a synchronous type DRAM), for example, transfers data to a function block such as a CPU in synchronism with a clock signal (100 MHz and 250 MHz), and receives data therefrom in synchronism with a clock signal.
The internal clock signal generated in the memory has a skew with, i.e., a small delay, with respect to the external clock signal supplied from the CPU to the memory. The skew causes a problem. Assume the external clock signal is a clock signal (100 MHz) which has a cycle of 10 nanosecond (nsec), and that the internal clock signal has a skew of 1 nsec with respect to the external clock signal. The skew amounts to 10% of the cycle of the external clock signal. Obviously, the skew of this value disables the memory from transferring data at high speed in synchronism with the external clock signal. In particular, the skew greatly affects the speed of transferring data from the memory to the function block, ultimately lengthening the data-reading time of the memory.
FIG. 1 shows a system in which data is transferred between a memory 11 and a CPU 12 in synchronism with a high-frequency clock signal. FIG. 2 represents the relationship between the external clock signal and the internal clock signal, both used in the system.
The memory is a synchronous type DRAM such as a synchronous DRAM. The memory 11 comprises a buffer 13, an input circuit 14, an output circuit 15, a write/read circuit 16, and a memory cell array 15.
The CPU 12 generates the external clock signal CK, which is input to the memory 11. In the memory 11, the buffer 13 converts the external clock signal CK to an internal clock signal CLK. The signal CLK is supplied to the input circuit 14, output circuit 15 and write/read circuit 16 to control the inputting of data to the memory cell array 17 and the outputting of data therefrom.
Generated by the buffer 13 from the external clock signal CK used as a trigger signal, the internal clock signal CLK inevitably has a skew with respect to the external clock signal CK. It is the internal clock CLK that controls the circuits 14 to 16. To transfer data between the memory 11 and the CPU 12, the circuits 14 to 16 must be controlled so as to compensate for the skew the signal CLK has with respect to the signal CK. This technique, however, results in a reduction of the data transfer speed.
Recently, various methods of minimizing or eliminating the skew have been developed. Two of these methods will be described below.
The first method is to use a PLL (Phase-Lock Loop) to detect the skew, and to feed the internal clock signal CLK back to the input of the buffer 13, thereby eliminating the skew. The method works well when the external clock signal CK is continuously supplied to the memory 11 and has a constant frequency.
The second method is to use a circuit which generates a corrected internal clock signal synchronous with the external clock signal in terms of timing. This method is considered desirable since the internal clock signal can immediately become synchronous with the external clock signal when the external clock signal changes in frequency or breaks off.
The principle of the second method will be explained, with reference to the timing chart of FIG. 3.
Assume the internal clock signal CLK has a skew D1 (delay) with respect to the external clock signal CK as shown in FIG. 3, and that both signals CLK and CK have a cycle T. A forward clock FCL is generated upon lapse of a period A from the leading edge of the first pulse of the internal clock signal CLK. Time .DELTA. elapses from the leading edge of the forward clock FCL to the leading edge of the second pulse of the internal clock signal CLK. Upon lapse of 2.DELTA. from the leading edge of the pulse FCL, a forward clock RCL is generated. Then, the period A starting from the leading edge of the pulse RCL terminates at the leading edge of the third pulse of the internal clock signal CLK, provided that (A+W)&lt;T, where W is the width of the forward clocks FCL and RCL.
Time D2 elapses from the leading edge of the forward clock RCL to the leading edge of the third pulse of the external clock signal CK. The forward clock RCL is delayed by the time D2, obtaining a corrected internal clock signal CK' which is synchronous with the external clock signal CK.
That is, the second method uses three delay circuits which provides the delay times A, 2.DELTA. and D2, respectively. The internal clock signal CLK is delayed by A+2.DELTA.+D2, thereby generating a corrected internal clock signal CK' which is synchronous with the external clock signal CK.
As can be understood from FIG. 3, A=D1+D2. The delay time D2 can be computed from the period A and the delay time D1. Since the cycle T of the external and internal clock signals CK and CLK is not constant, the time .DELTA. is not constant, either. One of the three delay circuits must therefore be designed to provide an accurate delay time 2.DELTA. in accordance with the non-constant cycle T of both clock signals CK and CLK.
The three delay circuits serve to generate a corrected internal clock signal the first pulse of which is synchronous with the third pulse of the external clock signal CK, irrespective of the cycle T of the external and internal clock signals CK and CLK. After the third pulse of the external clock signal CK, the corrected internal clock signal CK' remains synchronous with the external clock signal CK. Should the external clock signal CK break off, there can immediately be generated a corrected internal clock signal CK' which is synchronous with the external clock signal CK.
A clock control circuit which performs the second method will be described, with reference to FIG. 4.
As shown in FIG. 4, the circuit comprises an input terminal 21, a input buffer 22, a delay circuit 23, a forward delay array 24, a mirror control circuit 26, a rearward delay array 28, and a delay circuit 30. The forward delay array 24 is composed of a plurality of delay circuits 25-1, 25-2, . . . 25-n control circuit 26 has control elements 27-1, 27-2, . . . 27-n. The rearward delay array 28 is composed of a plurality of delay circuits 29-1, 29-2, . . . 29-n.
The external clock signal CK supplied to the input terminal 21 is input to the input buffer 22. The input buffer 22 outputs an internal clock signal CLK. Since the input buffer has a delay time D1, the internal clock signal CLK has a clock skew of D1 with respect to the external clock signal CK. The internal clock signal CLK is input to the forward delay array 24 through the delay circuit 23 which has a delay time A. The internal clock signal CLK is input to the mirror control circuit 26, too. The circuit 26 determines a delay time .DELTA.f of the forward delay array 24 and equalizes the delay time .DELTA.b of the rearward delay array 28 to the delay time .DELTA.f. The clock signal output from the rearward delay array 28 is supplied to the delay circuit 30 which has a delay time D2. The delay circuit 30 generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK.
The forward delay array 24 and the rearward delay array 28 are identical in structure, and the delay time .DELTA.f of the array 24 is used as the delay time .DELTA.b of the array 28. Thus, the delay arrays 24 and 28 provide a delay time of 2.DELTA., where .DELTA.=.DELTA.f=.DELTA.b.
In the clock control circuit of FIG. 4 it is difficult to render the delay time .DELTA.f and the delay time .DELTA.b completely the same, because forward pulses have a predetermined width. This problem will be explained below, with reference to FIG. 5.
FIG. 5 is a timing chart explaining how delay times .DELTA.f and .DELTA.b are determined at time t (FIG. 3) in the clock control circuit of FIG. 4.
As seen from FIG. 5, the forward delay array 24 remains active while a forward pulse is at "1" level; it remains inactive while the forward pulse is at "0" level. When the forward pulse is input to, for example, the delay circuit 25-k, the delay circuit 25-k is activated while all other delay circuits of the array 24 are deactivated. When a pulse of the internal clock signal CLK is generated thereafter, the kth delay circuit 29-k of the rearward delay array 28 is activated and generates a rearward pulse.
A forward pulse and a pulse of the internal clock signal CLK are input to the kth control element 27-k of the mirror control circuit 26. The control element 27-k activates the kth delay circuit 29-k of the rearward delay array 28. The delay circuit 29-k generates a rearward pulse. The control element 27-k which receives the forward pulse and the delay circuit which generates the rearward pulse assume the same place, i.e., the kth place. Therefore, the rearward pulse has its front edge F2 delayed with respect to the front edge F1 of the forward pulse by a time corresponding to the interval at which the delay circuits are arranged (for example, the width W of the forward pulse). Since the front edge F1 of the forward pulse and the front edge F2 of the rearward pulse determine the delay time .DELTA.f and the delay time .DELTA.b, respectively, the delay time .DELTA.b is shorter than the delay time .DELTA.f by, at most, the time corresponding to said interval.
As described above, the conventional clock control circuit performs the above-mentioned second method to generate a corrected internal clock signal synchronous with the external clock signal. However, none of the components of the clock control circuit can provide a predetermined delay time with accuracy. Consequently, it is difficult with the circuit to generate a corrected internal clock signal which is completely synchronous with the external clock signal.